The present invention relates to a lead frame, a semiconductor device, a method of manufacturing a lead frame, and a method of manufacturing a semiconductor device.
A lead frame for QFN (Quad Flat Non-leaded) packages or SON (Small Outline Non-leaded) packages is known in which a plurality of unit lead frames each having one die pad are formed. In the packaging process using such a lead frame, a semiconductor element is mounted over each of the unit lead frames before being resin-sealed and diced into separate unit lead frames.
In the technique which uses this kind of lead frame, it is desirable to provide a means to know where the unit lead frame of each separate semiconductor device after dicing was in the lead frame before dicing.
Japanese Unexamined Patent Publication No. 2004-193189 discloses a technique that for each semiconductor chip in a lead frame carrying a plurality of unit lead frames, the identification code of the semiconductor chip, the identification information of the lead frame carrying the semiconductor chip, the information on the location of the semiconductor chip in the lead frame and their mutual relation are stored and the identification information of the lead frame related to the semiconductor chip and the information on its location in the lead frame are printed on the back of the package of the semiconductor chip.
Japanese Unexamined Patent Publication No. 2003-124365 describes a method of providing semiconductor integrated circuit chip management information which includes the step of recording, for each of plural semiconductor integrated circuit chips formed in a semiconductor wafer, management information related to the manufacturing process of the semiconductor integrated circuit chip (date and time of production of the chip, lot number, wafer number, and location of the chip in the wafer, etc.) and the step of, when mounting a semiconductor integrated circuit chip separated from the semiconductor wafer over a lead frame, printing the management information on the lead frame in the vicinity of the area where the semiconductor integrated circuit chip is mounted.
Japanese Unexamined Patent Publication No. 2001-127236 describes an IC package produced by sealing a tab, inner leads and an IC chip mounted over the tab with transparent resin in which the inner leads have printing regions and a mark representing the manufacturer, a mark representing the product model number and/or a mark representing the manufacturing lot number are printed in the printing regions.
Japanese Unexamined Patent Publication No. Hei 5(1993)-36739 describes a semiconductor device manufacturing apparatus which bonds a semiconductor pellet to a lead frame and includes a printer module for printing the record of a die-bonded pellet on the back of the lead frame island on which the pellet is mounted.